The present invention relates to fabrication of semiconductor power devices.
More particularly the invention relates to fabrication of devices wherein a control electrode of silicided polysilicon is formed above a portion of semiconductor material which is laterally offset from source and DMOS channel regions of the device.
The invention relates also to a process for providing a semiconductor device with a control electrode consisting of self-aligned silicide and polycrystalline silicon, of the type in which said silicide layer is formed above the polycrystalline silicon following definition of active areas of the device formed on a portion of semiconductor material laterally with respect to said control electrode.
In the specific technological sector of the present invention it is well-known to use polycrystalline silicon or polysilicon to form the gate electrode of field-effect semiconductor devices, for example MOS transistors, which are also provided with source electrodes and drain. In the case of a vertical-current-flow DMOS device, the drain is not located at the front surface of the device.
Polycrystalline silicon offers several advantages compared to other materials and can be used to form both logic and analog integrated circuits as well as power devices.
Particularly with reference to power devices, it is known that they are formed by means of a multicellular structure which is derived from the ordered repetition of a basic cell. This cell can have a square, rectangular or hexagonal structure or any other suitable shape which is normally defined by means of openings formed in the polycrystalline gate electrode.
The power device can therefore be regarded as the result of a parallel connection of a large number of basic cells. In this context, the polycrystalline silicon gate electrode of each basic cell represents a first level of interconnection which is electrically insulated from an overlying metallization layer by means of an intermediate dielectric layer.
The metallization layer generally consists of aluminum and permits the formation of a source electrode which collects all the current which passes through the device, connecting together all the basic active areas. A small portion of the metallization area is used for biasing the gate electrode; this portion is separated by means of photolithographic techniques from the source electrode and is placed in direct contact with the polycrystalline silicon layer.
It is also well-known that the gate electrode is electrically insulated with respect to the underlying semiconductor substrate by means of a thin layer of silicon oxide. By varying the voltage of the gate electrode with respect to the source electrode it is possible to regulate conduction of the electronic device.
According to the physical principles which govern the operation of MOS devices, a capacitance which is not constant is present between the gate electrode and the source electrodes and drain. This parasitic capacitance requires a certain quantity of charge so that its potential can be varied.
The charge is supplied or recalled by an external circuit driving the gate electrode; in MOS power devices, the quantity of charge variation can be reach or exceed a few hundred nanocoulombs.
In order to obtain fast MOS devices, it is necessary to bias the gate electrode rapidly and uniformly. The commutation speed of these devices depends in fact also on the rapidity of changing the voltage of the gate, in particular for frequencies greater than 100 kHz. However, the gate electrode is subject to an RC time constant determined by the parasitic capacitance and parasitic series resistance of the gate electrode structure itself.
On account of the high resistivity of the polycrystalline silicon (.rho.=2-6 m.OMEGA.-cm) with respect to the distributed capacitance, the gate electrode during the commutation transient does not reach immediately and uniformly the same potential which is applied from outside via the driving circuit. Consequently, there will be a certain delay during charging up of the entire electrode; this delay will be all the more accentuated, the greater the distance between the basic cell and the contact termination of the metal gate electrode.
In an attempt to speed up and render uniform the polarization phase, the known art proposes a first solution which consists in sacrificing a part of the active area of the device in order to form an aluminum gate termination of suitable shape extending over most of the polycrystalline silicon area.
This particular aluminum termination normally assumes a fingered configuration and makes it possible to achieve a continuous contact with the underlying polycrystalline silicon layer.
Although advantageous in various respects, this solution does not resolve entirely the problem of speeding up the MOS devices and has the drawback that it requires active area to be sacrificed and places constraints on the topography of the metallization structure owing to the presence of the gate fingers.
A second solution proposed by the known art consists in attempting to reduce the sheet resistance of the polycrystalline silicon, forming above it a layer of a metal silicide.
Owing to the low resistivity of silicide (.rho.=17-150 .mu..OMEGA.-cm) compared to that of polysilicon and owing also to its greater thermal and chemical stability compared to pure metals, it is possible to integrate the suicides in the semiconductor devices into an intermediate phase of the production process; that is to say into a phase following which further heat treatments are envisaged.
Tungsten silicide is the material normally used for forming the silicide layer above the polycrystalline silicide by means of chemical vapor deposition (CVD) techniques.
The tungsten silicide cannot be obtained from the reaction between a tungsten film and the silicon, but it is necessary to deposit simultaneously both the atom species, tungsten (W) and silicon (Si).
This means that, contrary to that which occurs in the case of silicides obtained from the reaction of a metal film with silicon, the tungsten silicide layer must be defined by means of a photolithographic process. For this reason, the tungsten silicide layer is deposited after the polysilicon layer, then proceeding with etching of both the layers so as to obtain self-alignment.
Tungsten silicide, however, has disadvantages, one of which is a high resistivity (.rho.=100-150 .mu..OMEGA.-cm) which keeps the sheet resistance of the gate electrode high.
Moreover, as already mentioned above, the silicide is deposited onto the surface of the polysilicon before both the layers are defined by a photolithographic process. However, the MOS power devices are subjected to ion implantation and heat diffusion phases also following definition of the gate electrode. In particular, in the case of MOS power devices, the formation of the body and source junctions takes place following definition of the gate electrode and the presence of tungsten silicide on the surface of the polysilicon imposes some constraints on the production processes.
The known art has therefore proposed the use of alternative materials such as titanium silicide (TiSi.sub.2) or cobalt silicide (CoSi.sub.2), which have resistivities of between 17 and 20 .mu..OMEGA.-cm.
These silicides are normally obtained by reaction of a metal film with the silicon and are also defined "self-aligned" in that the reaction between the metal film deposited and the silicon takes place only when the two materials are brought into close contact. Consequently, if the semiconductor substrate is protected by an oxide layer in which some openings have been formed, then the formation of the compound will occur only inside these openings.
Titanium silicide and cobalt silicide have been proposed for the formation of structures such as that illustrated in FIG. 1.
This figure shows the basic cell of a MOS power device during an intermediate phase of the formation process, where a silicide layer is grown above the polysilicon gate electrode and also above the monocrystalline silicon regions.
The silicide layer is also used for the formation of ohmic contacts with the monocrystalline silicide above the active areas or regions of monocrystalline silicon. In order to ensure, however, insulation between the gate electrode and these active regions, oxide spacers have been provided along the perimeter of the electrode so as to prevent the formation of silicide on the side walls of the polysilicon.
On account of the chemical reaction between the metal and the semiconductor, which gives rise to the formation of silicide, the excess metal on the walls of the spacer may give rise to the formation of a metal compound with the silicon. The latter may in fact spread from the polycrystalline or monocrystalline region towards the side wall of the spacer.
This phenomenon, which has been extensively studied, is known in the literature as "lateral rising", and may be the cause of a short-circuit between the two layers of silicide deposited respectively above the polysilicon and above the active areas.
The danger of short-circuiting is due to the fact that the metal compound which rises up the spacers cannot be etched selectively with respect to the silicide, unlike that which is possible in the case of pure metal. If the metallic compound grown on the side wall of the spacer manages to electrically connect the two electrodes at any point on the perimeter, then the device will not function.
Therefore, the formation of the silicide on the surface of the monocrystalline silicon may be damaging on account of the phenomenon of lateral rising.
This fact must be duly taken into account when designing a MOS-type power device since, for reasons associated with the efficiency of the device, the channel perimeter which coincides substantially with that of the spacers tends to be maximized. In doing so, however, there may be a very high probability of a short-circuit occurring owing to the phenomenon of lateral rising, to the extent that the efficiency will be reduced.
Moreover, in a MOS power device, typically an N-channel MOS device, the formation of the silicide in the contact regions may be superfluous or deleterious, since the dimensions of the contacts are rarely less than a few microns. With dimensions of this order of magnitude, normal metallization with aluminum already enables a good ohmic contact to be formed both to n+ type semiconductors (for example the source region) and to the p-type semiconductors (for example the body region).
Instead, most of the suicides useful for these applications have the special characteristic that they produce a slight depletion of dopant atoms in the semiconductor near the silicide/silicon interface. This phenomenon has the effect of increasing the specific contact resistance between the silicide and the semiconductor.
This is particularly important for the p-type region (body) present inside the cell of an N-channel MOS transistor, or in the p-type region (emitter) in the case of an IGBT transistor. In the particular case of the MOS device, the body region forms the anode of a body/drain diode and this junction is used in some circuit applications as a "recirculation diode"; therefore, the drop in potential at its terminals when it is forward biased must be less than a predetermined value which depends on the type of device.
Self-aligned silicides could, owing to their low resistivity, be used in place of tungsten silicide by growing these materials soon after the deposition of the layer of polycrystalline silicon. Subsequently, via a photolithographic process, openings in the gate electrode may be defined. However, since these materials have a thermal stability which is lower than that of tungsten silicide, their integrity would be affected by the subsequent heat processes required for completion of the device.
The technical problem underlying the present invention is that of devising a semiconductor device, in particular a field-effect power device, having structural and functional characteristics such as to enable a control electrode consisting of self-aligned silicide and polycrystalline silicon to be obtained, overcoming the limitations and/or the drawbacks indicated previously with respect to the known art.
The present application discloses the novel idea of forming a gate electrode with a double layer of polysilicon and cobalt silicide, the latter being obtained by means of a direct reaction between cobalt and silicon precisely and only in the region of the gate electrode, while the active areas of the device are protected from this reaction.
The silicide is preferably cobalt silicide, which has a low resistivity value (between 17 and 20 .mu..OMEGA.-cm). Cobalt silicide has been found to be highly preferred over titanium silicide, for the following reasons:
Titanium reacts strongly with oxygen (so much so that in the field of ultra high vacuum apparatus titanium has been used to implement pumps to improve the vacuum conditions). This implies that the deposition of titanium must be done using equipment which would provide a very high base vacuum level, to avoid inclusion of oxygen in the interior of the film. Cobalt, being a metal of the "near noble" class, does not present this inconvenience. PA1 For the same reasons, the ambient within which the reaction between the metal and silicon is performed ("RTA," i.e. rapid thermal annealing) must, in the case of titanium, be extremely tightly controlled. Very small percentages of oxygen can indeed oxidize the surface of the metal or directly inhibit the reaction necessary for formation of the silicide. PA1 The silicide of cobalt (CoSi.sub.2) is more thermally stable. That is, this material, as compared with titanium silicide, is less susceptible to the phenomenon of "balling up." This phenomenon appears when a silicide film is exposed to high temperature processes, particularly if the silicide film was grown from a layer of polycrystalline silicon. At high temperature the individual grains of the silicide separate, and assume the shape of microspheres which are included in the interior of the semiconductor. This has the effect of significantly increasing the sheet resistance of the film, since the film is no longer continuous. Obviously this phenomenon is disadvantageous in all those applications where the silicide film is used to reduce the sheet resistance of an underlying film of polycrystalline silicon. The thermal budget item which can be very inconvenient in general is the high-temperature time necessary for reflowing the dielectric layer. (layer 13 in FIG. 9). This procedure serves to soften the topology resulting from the sidewall of the patterned polysilicon layer, so as to provide more margin for the metallization process. To facilitate the reflow of the interlevel dielectric, it is well known that phosphorus doped oxide (PVAPOX) or borophosphosilicate glass (BPSG) can be used.
The aluminum source metallization is normally doped with silicon, because the metal is in direct contact with the semiconductor source and body regions. This alloy serves to eliminate the well known phenomenon of spiking, where aluminum intrusions may perforate the underlying junctions. However, this alloy incurs problems when deposition temperatures above 350 to 400 degrees C. are used. Such temperatures are necessary to provide optimal step coverage of the metallization over the topographical gradients present in the underlying structure. However, under such deposition conditions there have been measured an excessive number of silicon precipitates (derived from the silicon originally present in the alloy), which are type P+ due to aluminum doping, and which can partially block the contact. For this reason the deposition temperature must be maintained below 300 degrees C., and moreover the underlying structure must not present any sharp topography.
Nevertheless, the process of reflow is very important, and cannot be done in a furnace, since the duration of heating will degrade the characteristics of the silicide.
After vapor-phase deposition of vapox/BPSG (BPSG is the material which reflows at the lowest temperature) over the sharp slopes due to the side walls of the polysilicon layer, the as-deposited angles will actually be negative (in relation to the normal from the surface of the semiconductor and the tangent to the side wall of the polysilicon). In the example of FIG. 12, this angle is -20.degree.. This prejudices the step coverage of the metallization, and a reflow process is therefore necessary.
The reflow can be performed under RTA conditions, and it has been experimentally confirmed that, in order to use metal deposition temperatures around 200 degrees C., the reflow must attain positive angles greater than 20 degrees. From the experimental graph of FIG. 13 attached, where this angle is shown as a function of temperature, it may be seen that reflow temperatures must be at least 950 degrees to obtain such angles. Such temperatures, as seen in FIG. 11, are dangerously close to the stability limit of titanium silicide.